This specification relates to polishing pads useful for polishing and planarizing substrates, such as semiconductor substrates or magnetic disks.
Polymeric polishing pads, such as polyurethane, polyamide, polybutadiene and polyolefin polishing pads represent commercially available materials for substrate planarization in the rapidly evolving electronics industry. Electronics industry substrates requiring planarization include silicon wafers, patterned wafers, flat panel displays and magnetic storage disks. In addition to planarization, it is essential that the polishing pad not introduce excessive numbers of defects, such as scratches or other wafer non-uniformities. Furthermore, the continued advancement of the electronics industry is placing greater demands on the planarization and defectivity capabilities of polishing pads.
For example, the production of semiconductors typically involves several chemical mechanical planarization (CMP) processes. In each CMP process, a polishing pad in combination with a polishing solution, such as an abrasive-containing polishing slurry or an abrasive-free reactive liquid, removes excess material in a manner that planarizes or maintains flatness for receipt of a subsequent layer. The stacking of these layers combines in a manner that forms an integrated circuit. The fabrication of these semiconductor devices continues to become more complex due to requirements for devices with higher operating speeds, lower leakage currents and reduced power consumption. In terms of device architecture, this translates to finer feature geometries and increased numbers of metallization levels. These increasingly stringent device design requirements are driving the adoption of smaller and smaller line spacing with a corresponding increase in pattern density. The devices' smaller scale and increased complexity have led to greater demands on CMP consumables, such as polishing pads and polishing solutions. In addition, as integrated circuits' feature sizes decrease, CMP-induced defectivity, such as, scratching becomes a greater issue. Furthermore, integrated circuits' decreasing film thickness requires improvements in defectivity while simultaneously providing acceptable topography to a wafer substrate; these topography requirements demand increasingly stringent planarity, line dishing and small feature array erosion polishing specifications.
Historically, cast polyurethane polishing pads have provided the mechanical integrity and chemical resistance for most polishing operations used to fabricate integrated circuits. Typical pads rely upon a combination of porosity, macrogrooves or perforations and diamond conditioning to create a surface texture that improves wafer uniformity and material removal rate. Diamond conditioning may occur on a periodic “ex situ” basis or a continuous “in situ” basis to maintain steady state polishing performance—the absence of conditioning will result in the pad glazing and losing its polishing ability. As polishing standards have tightened over the years, the vast majority of fabs rely upon in situ conditioning to maintain acceptable removal rates. In addition, fabs have moved to more aggressive diamond conditioning to achieve increased stability and increased removal rates.
Lawing, in U.S. Pat. No. 6,899,612, discloses a surface morphology through controlled diamond conditioning for optimizing a polishing pad's planarization performance. In addition to optimizing conditioning for polishing performance, next generation polishing pads contain specialized polymer matrices that achieve a combination of excellent planarization and low wafer defectivity. Unfortunately, some of these high performance polishing pads lack acceptable polishing performance, such as removal rate for the most demanding polishing applications. There is a desire for improving the polishing performance of these high performance polishing pads.